1. Field of the Invention
The present invention relates to a method for fabricating a storage electrode of a dynamic random access memory (DRAM) cell.
2. Description of the Prior Art
As the integration degree of a DRAM cell increases, sufficient amount of electric charge is required for operation of the DRAM cell. To this end, the DRAM cell includes a storage electrode stacked in a three dimensional structure.
FIG. 1 illustrates a DRAM cell having a storage electrode of a stacked structure in the general type as follows.
A field oxide film 2 is formed on a predetermined portion of a silicon substrate 1; over the silicon substrate 1, numerous MOSFETs are then formed, each of which includes a gate oxide film 3, a gate electrode 4, and diffusion regions 5A and 5B for a source and a drain; an insulating film 6 is formed around each gate electrode 4; a bit line 7 is then formed which is connected to the diffusion region 5A; over the entire surface of the resulting structure, an insulating layer 8, for example a BPSG layer, showing a good flow characteristic is formed; over the insulating layer 8, an inner insulating layer 9, for example interpolyoxide, is then formed; thereafter, the inner insulating layer 9 and the insulating layer 8 are etched at their portions disposed over each diffusion region 5B so as to form contact holes and a storage electrode 10 of polysilicon layer is finally formed which is in contact with each diffusion region 5B.
The structure fabricated in a manner as mentioned above has a high aspect rate a/b between the height "a" and the width "b" of the contact hole which is for contact with the storage electrode. This aspect rate becomes higher at a higher integration degree.
On the other hand, the storage electrode is mainly comprised of a polysilicon layer. The polysilicon layer is doped with impurities by use of an ion implantation process or a POCl.sub.3 doping process so that the storage electrode has a desired resistance.
However, it is difficult to make resistance uniformly by doping impurities uniformly in the polysilicon layer for the storage electrode embedded in a contact hole showing a high aspect rate.
For uniformly doping the impurities in the polysilicon layer, an in-situ process has been proposed. In accordance with the in-situ process, the impurities are doped in a polysilicon layer at the same time the poly-silicon layer is being deposited. In order to form a storage electrode having a low resistance, high concentration impurities should be implanted in a polysilicon layer. In this case, however, the impurities implanted in the polysilicon layer may be excessively diffused in diffusion regions for source and drain on the bottom of a contact hole when a subsequent thermal process is performed, so that the diffusion regions may be enlarged to the dotted range, as shown in FIG. 1. As a result, the channel length of each MOSFET becomes short. This raises a problem in operation of a device finally produced, such as a variation in threshold voltage.